Avatar Integrated Systems Helps Tackle Advanced Node and Extreme Low Power Design Challenges with Aprisa 19.1 Release

Breakthrough routing and power features help designers improve
performance, capacity, low power and area concerns

SANTA CLARA, Calif.–(BUSINESS WIRE)–Avatar Integrated Systems, a leader in next-generation physical design
solutions, today announced it has added major new features to its
Aprisa™ place & route solution. Avatar introduced Sibling Routing™ and
PowerFirst™ technologies in the upcoming Aprisa 19.1 release, two
technologies designed to address the performance and capacity challenges
of place and route at advanced process nodes, and the demands for
extreme low power and smaller silicon area at mainstream nodes.

This latest innovation demonstrates Avatar’s dedication to helping
designers overcome some of the most daunting challenges in integrated
circuit design today. For example, there’s increased design complexity
as well as ceaseless demand for faster computation speed in applications
such as cloud computing, AI, ML, mobile, 5G, and other areas. This has
spurred many companies to more quickly adopt advanced process nodes with
more complex technology constraints and new design challenges.

On the other hand, emerging application areas such as Internet-of-Things
(IoT), edge computing, and battery-powered devices, require extremely
low stand-by and active mode power consumption.

“The 19.1 release is an evidence of our continuous technology innovation
in digital place and route,” said Ping-San Tzeng, CTO of Avatar
Integrated Systems. “We are confident that the 7FF certification,
Sibling Routing, and PowerFirst technology will greatly help our user to
achieve their design successes.”

The Aprisa 19.1 release includes many features that dramatically improve
the runtime, capacity, design convergence, and the final quality of
results (performance, power, area) of the designs. In particular, the
new release introduces the following unique technologies:

  • Release 19.1 includes support for TSMC 7FF technology node.
    Avatar collaborated with TSMC to complete rigorous
    certification
    tasks to ensure full support of the 7nm FF node in
    the area of design enablement, reference flow, correlation with
    signoff, and quality-of-results. All 7FF design collaterals are now
    available for immediate design start.
  • Sibling Routing technology. At advanced process nodes, such as
    7nm, the impact of high resistivity of wires and vias at lower metal
    layers can cause timing and electromigration (EM) issues. Avatar’s
    patented Sibling Routing is an innovative technology that addresses
    those issues. Sibling Routing uses multiple wires and vias to connect
    a single net at lower layers, rather than single wire and single via,
    which is found in traditional routers. The new routing model provides
    lower net resistivity, which results in improved timing, higher clock
    speed, and better routability and EM reliability.
  • Release 19.1 also introduces PowerFirst technology for
    extreme low-power design at any node. In traditional design
    techniques, conventional place-and-route algorithms tend to focus on
    maximizing design performance (timing), while minimize power and area
    as much as possible. This approach often leads to over-design for
    timing, while leaving much power saving on the table. Avatar’s
    PowerFirst technology puts power front-and-center of the design
    target. It optimizes the designs for the lowest power first, then
    makes necessary tradeoff to meet timing. The technology includes a
    suite of features spanning the entire design flow, covering both
    standby power and active-mode power. It is the optimal place-and-route
    technology for today’s power-sensitive designs.

Visit Avatar in Booth #967 at the upcoming Design
Automation Conference (DAC)
to learn more about Aprisa’s Sibling
Routing technology and PowerFirst. Sign up today for a private
demo
with Avatar at DAC. The 56th DAC will be held in the
Las Vegas Convention Center in Las Vegas, Nevada from Sunday, June 2 to
Thursday, June 6.

About Avatar Integrated Systems

Avatar Integrated Systems is a leading software company in the
Electronic Design Automation (EDA) industry focused on Physical Design
Implementation. The company’s products enable integrated circuit (IC)
designers to create semiconductor chips, which enable today’s electronic
devices, such as smartphones, computers, internet equipment, IoT
wearables, etc. Avatar’s products are built on the proven technologies
acquired from ATopTech, Inc. Avatar Integrated Systems is headquartered
in Santa Clara, Calif. with subsidiaries and offices in Taiwan, India,
Japan, and Korea. The company continues to serve global customers with
cutting-edge digital place-and-route technology and closely partners
with customers to reach their design successes. For more information
visit: www.avatar-da.com.

Contacts

Michelle Clancy
Cayenne Communication
503 702 4732
[email protected]

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